The invention relates to a Flash memory for standard applications, integrated with a LPC interface block and of the type comprising a memory block or Flash core which includes a matrix of non-volatile memory cells, with associated circuit portions for reading, modifying and erasing the data contained in the memory, and an interface block associated with the LPC communication interface and comprising at least an address block, a data block and a state machine which enables the flow of data from and towards the memory block on respective address bus and data bus. The applicable integrated electronic memory device is a non-volatile memory of the Flash EEPROM type to be installed on a motherboard for PC applications on a PCI bus and it has eleven external address pins, eight data pins and some control pins among which the synchronism or clock signal CLK and a setting signal of the two IC interfaces.
Typically, the memory device is provided with two communication interfaces: a parallel or pseudo-parallel interface, such as A/Amux interface, and a serial or LPC interface. The first one is thought to perform quick pre-programming and testing operations whereas the second one is used during the normal operation of the personal computer according to a well established communication protocol. A selection signal, called IC, which allows to switch from an operation interface to the other one is provided. All the addresses and all the data considered are managed in a parallel mode, whereas only the clock signal CLK and other four control pins are necessary for the communication serial protocol.
FIG. 1 schematically shows the structure of a motherboard of a computer 1 of the PC type. As seen in FIG. 1, the blocks 2 and 3, labeled I/O Controller and Memory Controller, are provided to put a processor 10 of the motherboard and the system peripherals 6, 7 in communication with a memory 5, where the device operative system BIOS is stored; this occurs for each type of operation. The other blocks 8, 9 of the system are those allowing the computer 1 to interface with the external world and they are here highlighted only by way of description.
In this specific technical field it is well known that the read operation of a memory location of a cell matrix first implies the passage of the address of the location itself. The block provided for the management of the addressing in the available memory space is the Memory Controller 3. FIG. 2 shows a block scheme of a memory device to which the present invention is applied. Such a device, inserted and supplied between two voltage references Vdd and GND, has four Input/Output Lpc <3:0> pins through which all information are exchanged and a further pin called Lframe which allows to enable the memory to receive the protocol, besides a clock pin.
FIG. 3 shows the pattern in time of the timing signals for the execution of a read operation (Read) of the memory in the Low Pin Count mode. Similarly, FIG. 4 shows the pattern in time of timing signals for the execution of a write operation (Write) of the memory in the Low Pin Count mode. During the period when the Lframe signal is low, the Start command is decoded, a Cycle Type cycle follows which distinguishes between the request for a read operation (Read) and a write one (Write). The successive eight clock counts are dedicated to the address memorization.
In a Read operation there are thus two signal cycles Tar during which the system host transfers the external bus control to the memory, which, to synchronize the output data, generates Sync cycles before the real data. The operation ends with two further cycles Tar during which the memory transfers again the bus control to the host.
In a Write operation, instead, after having supplied it with the memory addresses, the system host supplies the memory with two nibbles of the data to be programmed. The system host will thus transfer the control to the memory during two Tar cycles. The memory starts then the inner write operations and responds on the buses with a wait cycle (Sync) and further Tar cycles for transferring again the bus control.
The device of the prior art is characterized by an architecture of the single bank type which allows to perform one operation at any one time, in the sense that if during a modify operation the user would go and read a memory location he would have to first interrupt the on-going modify operation and immediately perform the read operation. This limits the device and makes the device inflexible.
FIG. 5 shows a block scheme of the architecture of a device according to the prior art and operating as previously described. Two main macro blocks can be distinguished, the interface block 10 and that of a standard Flash memory 11 here called Flash Core. In the interface 10, a block 17 Cycle Type receives the clock signal and the information inputs Lpc<3:0> and it distinguishes between a read and a write request, these information being passed to an inner state machine 12 provided to scan the various steps of the communication protocol. This state machine 12 generates the enable signal which allows the addresses memorized in the block 13 Addlatched to transfer an enable signal for the data and a write enable signal into the Flash core 10.
The data being read come from a read amplifier 14, or Sense Amp, to a DataI block 15 to be memorized and then sent out synchronized with the clock, those being written instead are first memorized in the DataI block and then sent into the Flash core to go to the CUI (Command User Interface) block if it is a command or directly to the Sense Amps in case it is information to be programmed.
FIG. 6 finally shows the schematic structure of a memory device of the known single bank type wherein the sense amplifiers are highlighted each one being associated with a half-matrix of cells. The presence is to be noted of a single block of reference cells to be used by both the half-matrixes, the right one and the left one.
The technical problem underlying the present invention is that of providing a memory electronic device with a serial interface of the LPC type and having such structural and functional characteristics as to allow to accede to the memory in an independent way to simultaneously perform read and write operations overcoming the limits of the known approaches.